Recent Projects:

• High Speed Serial Links DFT & MFG Test, 3rd Party IP (PCIe, SATA, XAUI, DDR3, USB, XIO, ...) mixed-signal Mfg test Architecture Development & DFT/MFT Technical Lead
  3rd Party IPs: ARM 80nm PCIe 3G, Synopsys 80nm DDR3/2, Synopsys 65nm PCIe1 3G, Synopsys 65nm PCIe2 6G, Synopsys 45nm PCIe3 8G
• Mix-Signal IP Acquisition & Verification:, 3rd party Silicon IP Qualification, Certification and Release Standards and Methodology
• System-On-a-Chip Verification: Assertion-based SOC Verification, Web-based Silicon IP Analysis and Acqusition
• Functional Verification Coverage Analysis: Coverage Driven Verification (CDV) of Advanced PowerPC Embedded Microprocessors, Coverage Driven test Generation (CDG)
• System-On-a-Chip: Modeling, Analysis and Modular Design Methodology
• Processor Functional Verification Test Generators: RTPG/MP_RTPG/MPTG/MBTG/Genie test case generation
• Multi-Processing Coherency & Functional Verification: PowerPC 740 (Mach5), PowerPC 750 (Arthur), PowerPC G4 (C4)
• Processor Functional Verification: PowerPC 604 (Zephyr), PowerPC 604e (Windstormr), PowerPC 740 (Mach5), PowerPC 750 (Arthur), PowerPC G4 (C4)
• Knowledge-Based Multimedia Systems: Expermedia/2 for semiconductor manufacturing control & optimization
• Logic Synthesis: LTS & LSS for Auto Logic Synthesis and Optimization from Netlist
• Technology Mapping: TMS for Auto conversion of Bipolar Netlist(s) to CMOS Netlist
• Logic Design: PLA, CVS, Standard Cells, Memory
• Circuit Design and Physical layout: